Modern electronics, particularly integrated circuits (IC), often contain phase-locked loops (PLL) for providing frequency clocks to the IC. A PLL is a closed loop frequency control system that operates on the phased sensitive detection of phase difference between two signals, the reference signal and a feedback signal. Upon activation, a certain amount of time is needed in order for the PLL to settle in to a stable and locked frequency. This settling time varies, but it is important for the PLL to stabilize before its output may be used.
One solution to having a stable PLL output is to simulate the PLL and find the point at which it reaches stability, or lock, in varying conditions. By taking the worst case scenario, and adding some safety margin, a default waiting period may be established after which its assumed the PLL output is stable and may be used. One problem with this is that the PLL may cycle in a locked mode for some period of time before its output is used, delaying execution of the IC function.
Another solution, which implements analog circuits, uses a phase frequency detector to determine when a PLL is locked. However, combining analog circuits with digital circuits is complex.
A third solution clocks a counter by the reference signal and a counter by the feedback signal, while a control unit enables both counters for a defined time interval. At the end of the time interval, the control unit compares the output of the two counters, and asserts a phase lock indicator if the counts are equal. One problem with this solution is that it requires several components and is complex.
Accordingly, what is needed is a method and system for a lock detector that can be added to an existing PLL system that is simple to implement. The present invention addresses such a need.